In the manufacturing of an integrated circuit (IC) using Metal-Oxide-Semiconductor (MOS) technology, processes involving charged ions are typically employed, such as a plasma etching process and an ion implantation process. As an example, during a plasma etching process used in forming gate polysilicon (poly) patterns or interconnect metal line patterns, electrostatic charges may accumulate on a floating gate poly electrode. The resulting voltage on the gate poly electrode may become so large that charges may flow into the gate oxide, become trapped in the gate oxide or flow through the gate oxide. These charges may significantly degrade the gate oxide strength and cause MOS device reliability failures.
Each poly gate region collects an electrostatic charge proportional to its own area. A small gate oxide region connected to a large poly geometry or a large interconnect metal geometry through poly contacts can accumulate a disproportionate amount of charges (positive plasma ions in the case of a grounded or a negative biased wafer) and may suffer serious damage. This mechanism is commonly known as the antenna effect because the large poly or interconnect metal area act as an antenna to collect the electrostatic charges that flow through the vulnerable gate oxide. The strength of the antenna effect is proportional to the ratio between the exposed conductor area and the gate oxide area.
FIG. 1 is a schematic top view of a portion of an IC, illustrating existing techniques involved in preventing antenna effect. PMOS transistor P1 is formed in N-well 8 in a semiconductor substrate. Gate electrode 12 of P1 is electrically connected to a long poly line 14. Poly line 14 is electrically connected to a long metal line 16 in the first interconnect metal layer through poly contact 11. Line 16 may be, in turn, electrically connected to metal lines in the upper interconnect layers, and, eventually, to chip pad 25 where outside electrical signals may are received and the processed electrical signals may be transferred back. As a first effort in preventing antenna effect on the long geometry of poly line 14 and metal line 16, a reverse-biased diode D1 may be added between poly line 14 and N-well 10 formed in the semiconductor substrate. Diode D1 typically has a minimum-size so that breakdown on it occurs prior to an antenna effect on poly gate 12 when excessive charges are accumulated on poly line 14 during a plasma etch process, for example.
As another effort in preventing antenna effect, antenna design rules are commonly imposed on antennas, such as such as poly line 14 and metal line 16 in FIG. 1. When the antenna-to-gate area exceeds a pre-determined ratio, the excessive antenna area is divided into separated sections, each section having an area conforming to the antenna design rule. Antenna effects may be eliminated when forming the separated poly or interconnect metal sections in a lower interconnect layer. These separately-formed poly or metal pieces may be electrically coupled together in later processing steps through metal jumpers formed in an upper interconnect layers of an IC, such as metal bridge 20 in the second interconnect metal layer, where vias 13 are used to join metal line 16 in the first interconnect metal layer and metal jumper 20 in the second interconnect metal layer.
While the feature sizes in an IC, such as the gate dimension of an MOS transistor and the critical dimensions of an interconnect line, continue to shrink in advanced technology, less scaling has been done on the dimensions of the chip pads in an IC. This is because the dimensions of a chip pad on an IC need to be inherently large enough to facilitate access by external means during the course of IC fabrication. As an example, a chip pad should be large enough to facilitate an IC packaging process where metal wires are bonded to the chip pads via mechanical means. As another example, a chip pad should have ample area for the landing of a test probe that applies test stimuli from an IC tester during an IC test process. Thus, the trend of device feature-size scaling will aggravate antenna effect associated with an IC chip pad.
Although being effective in interconnect metal layers, the diode-dropping and the metal jumper scheme described above are less effective in preventing antenna effect associated with chip pads on an IC for at least the following reasons. First, the diode drop scheme may require changing the original circuit topology in an IC, thus affecting circuit performance. More details in this regard will be explained in the coming descriptions. Second, the bonding surface of a chip pad is typically formed in the uppermost conductive pad layer, therefore forming metal jumpers from thereon is not feasible.